Verification and Validation – a design process afterthought, or a first class citizen?
Validation in embedded software systems should be weaved into the design process itself. Reliable embedded system design process entails validation throughout the design process, starting from model validation where we zoom into system behavior modeling, simulation and formal finite state-machines. The test cases extracted from the model testing process are implemented and executed for the system – hence formal methods merge into informal methods of testing gradually. Formal verification include mathematical proof of correctness and guarantees, and it reliably confirms system behavior on all possible inputs, while also satisfying the requirements of system where exhaustive testing is inefficient or may be infeasible for all inputs. The formal verification includes providing possible algorithmic guarantees, for example, upper and/or lower bound on the execution time for a given part of the code. For functionality simulation, we deploy simulation models that simulate the actual system for selected inputs. Simulation includes performance simulations when the actual platform of execution isn’t available for decisions to go through. In all cases though, positioning of resultant escalated risks indicates the decision swings from team leads to project leads in one form of the other – which further solidifies the argument that verification and validation are definitely a first class citizen of system design process.